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1 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary nc ce1# nc a20 a19 a18 a17 a16 v cc a15 a14 a13 a12 ce0# v pp rp# a11 a10 a9 a8 v ss a7 a6 a5 a4 a3 a2 a1 wp# we# oe# sts dq15 dq7 dq14 dq6 v ss dq13 dq5 dq12 dq4 v cc v ss dq11 dq3 dq10 dq2 v cc dq9 dq1 dq8 dq0 a0 byte# nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 flash memory general description the MT28F160S3 is a nonvolatile, electrically block- erasable (flash), programmable, memory containing 16,777,216 bits organized as 2,097,152 bytes (8 bits) or 1,048,576 words (16 bits). the 16mb device is organized as thirty-two 64kb erase blocks and features in-system block locking that is either lockable or unlockable, selectively and individually. pin assignment (top view) MT28F160S3 56-pin tsop note: the # symbol indicates signal is active low. the MT28F160S3 also features a common flash interface (cfi) that permits software algorithm for the device. the software is device-independent and jedec id-independent, with forward and backward compat- ibility. additionally, the scalable command set (scs) allows a single, simple software driver in all host systems to work with all scs-compliant flash memory devices. the scs provides the fastest system/device data transfer rates and minimizes the device and system-level implementation costs. features ? x8/x16 organization ? thirty-two 64kb erase blocks ?v cc and v pp voltages: 3vC3.6v v cc operation, 75ns (min) access time 2.7vC3.6v v cc operation, 100ns (min) access time 2.7vC5v i/o capable* 2.7vC3.6v, or 5v v pp application programming ? enhanced data protection feature with v pp flexible sector locking sector erase/program lockout during power transition ? industry-standard pinout ? inputs and outputs that are fully ttl-compatible ? common flash interface (cfi) and scalable command set (scs) ? deep power-down: i cc = 15a ? automatic write and erase algorithm ? 2.7s per byte effective programming time using write buffer ? automatic suspend options: block erase suspend-to-read block erase suspend-to-program program suspend-to-read options marking ? timing 75ns access -75 100ns access -10 ? package plastic 56-pin tsop type 1 rg * 5v i/o is a manufacturing option. contact factory for availability. part number example: MT28F160S3rg-10
2 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary general description (continued) to achieve optimization of the processor-memory interface, the device accommodates v pp , which is either switchable during block erase, program, or lock bit configuration or is hardwired to v cc , depending on the application. v pp is treated as an input pin to enable erasing, programming, and block locking. when v pp is lower than the write lockout voltage, v lko , all program functions are disabled. each block of the device can be independently erased 100,000 times. in addition, program suspend mode allows system software to suspend programming to read data from other flash memory locations. additionally, the device offers individual block locking, which is controlled through a combination of block lock bits. block erase suspend allows the reading of data from or the programming of data to any other block. the status pin (sts) provides a logic signal output that acts as an additional indicator of internal state machine (ism) activity. this status indicator minimizes both cpu overhead and system power consumption. in the default mode, it acts as a ry/by# pin. when low, sts indicates that the ism is performing a block erase, program, or lock bit configuration. when high, sts indicates that the ism is ready for a new command. two chip enable pins (ce#) are used for enabling and disabling the device to activate the control logic, input buffer, decoders, and sense amplifiers. the byte# pin allows x8 or x16 reads/writes to be selected. byte# at logic low selects an 8-bit mode using address a0 to select between the low byte and the high byte. byte# at logic high enables 16-bit operation. y - select gates sense amplifiers write/erase-bit compare and verify addr. buffer/ latch power (current) control addr. counter i/o control logic v pp switch/ pump status register identification register y - decoder x - decoder/block erase control state machine a0-a20 oe# we# rp# v pp dq0-dq15 8 8 ce0# 8 output buffer input buffer write buffer v cc sts# 64kb memory block (0) 64kb memory block (31) 64kb memory block (1) 64kb memory block (2) 64kb memory block (29) 64kb memory block (30) 8 query byte# ce1# wp# command execution logic functional block diagram
3 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary pin descriptions 56-pin tsop numbers symbol type description 55 we# input write enable: determines if a given cycle is a write cycle. if we# is low, the cycle is either a write to the command execution logic (cel) or to the memory array. 14, 2 ce0#, ce1# input chip enable: with ce0# or ce1# high, the device is deselected and power consumption is reduced to standby levels. both ce0# and ce1# must be low to select the device. all timing specifications are the same for these two signals. 16 rp# input reset/power-down: when low, rp# clears the status register, sets the ism to the array read mode, and places the device in deep power-down mode. all inputs, including ce0#/ce1#, are dont care, and all outputs are high-z. rp# must be held at v ih during all other modes of operation. 54 oe# input output enable: enables data ouput buffers when low. when oe# is high, the output buffers are disabled. 56 wp# input write protect: controls the lock down function of the flexible locking feature. when low, locked blocks cannot be erased or programmed, and block lock bits may not be altered. 32, 28, 27, 26, 25, 24, a0-a20 input address inputs during read and write operations. a0 is only 23, 22, 20, 19, 18, 17, used in the x8 mode. 13, 12, 11, 10, 8, 7, 6, 5, 4 31 byte# input byte enable: when low, byte# places the device in the x8 mode. when high, byte# places the device in the x16 mode and ignores the a0 input buffer. address a1 then becomes the lowest order address. 15 v pp input programming voltage: necessary voltage for erasing blocks, programming data, or configuring lock bits. typically, v pp is connected to v cc . 33, 35, 38, 40, 44, 46, dq0-dq15 input/ data i/o: data output pins during any read operation or data 49, 51, 34, 36, 39, 41, output input pins during a write. 45, 47, 50, 52 53 sts output status: indicates the status of the ism. when configured in its pulse mode, it can pulse to indicate program and/or erase completion. when configured in level mode (default), it acts as a ry/by# pin. 9, 37, 43 v cc supply supply power: 2.7vC3.6v. 21, 42, 48 v ss supply ground. 1, 3, 29, 30 nc C no connect: these pins may be driven or left unconnected.
4 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary operation overview the mt28f10s3 device has an on-chip internal state machine (ism) for block erase and programming man- agement, and lock bit configuration. the device de- faults to read array mode upon initial device power-up or return from deep power-down mode. the external memory control pins allows array read, standby, and output disable operations. read array, status register, query, and identifier codes can be accessed through the command execution logic (cel), which is independent of the v pp voltage. proper programming voltage on v pp enables successful block erasure, program, and lock bit configuration. all block erase, program, and lock bit configuration functions are accessed via the cel and verified through the status register. commands are written with standard micro- processor write timings. the cel contents become an input to the ism that controls the block erase, program- ming, and lock bit configuration. the ism regulates the internal algorithms, including pulse repetition, internal verification, and data margining. during write cycles, addresses and data are internally latched. writing the appropriate command outputs array data, identifier codes, or status register data. interface software that initiates block erase, programming, and lock bit con- figuration can be stored in any block. during memory update, this code is transferred to and executed from the system ram. upon successful completion of an update, reads are again possible via the read array command. block erase suspend allows system software to suspend a block erase to read data from, or program data to, any other block. program suspend allows system software to suspend a program to read data from any other flash memory location. data protection the system designer may choose to make the v pp power supply switchable or hardwired to v pph 1/2/3 , depending on the application. using either configura- tion will enable designers to optimize the processor- memory interface. when v pp is lower than v pplk , memory contents are fixed. when v pp is high, the two-step block erase, program, or lock bit configuration command sequences provide data protection. when v cc voltage is below the write lockout voltage v lko , or when rp# is at v il , all write functions are disabled. the device can lock blocks to provide additional protection from unwanted code or data changes. bus operation all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. read reading the device is independent of the applied v pp voltage and users can obtain block information, query information, identifier codes, and status register set- tings. to read, the device must be first placed into the desired read mode. this can be done by writing the appropriate read mode command (read array, query, read identifier codes, or read status register) to the cel. the device will automatically reset to read array mode upon initial device power-up or after exit from deep power-down mode. control pins manage the data flow in and out of the component. ce0#, ce1#, and oe# must be driven active to obtain data at the outputs. ce0# and ce1# are the device selection controls, and when both are active, they enable the selected memory device. oe# is the data output (dq0Cdq15) control. when active, it drives the selected memory data onto the i/o bus. both we# and rp# must be at v ih . the read operations timing diagram illustrates a read cycle. output disable when oe# is at a logic high level (v ih ), the device outputs are disabled. standby when the device is in standby mode and ce0# or ce1# are at a logic high level (v ih ), the device power consumption is substantially reduced. dq0-dq15 (or dq0-dq7 in x8 mode) outputs are high-z, indepen- dent of oe#. when deselected during block erase, programming, or lock bit configuration, the device continues its operation and consumes active power until operation completion. deep power-down the deep power-down mode occurs when rp# is at v il . rp# low deselects the memory, places output drivers in high-z, and turns off all internal circuits. rp# must be held low for time t plph. a period of t phqv is required after power-down before initial memory access outputs are valid. after this wake-up interval, normal operation is resumed. the cel resets to read array mode, and the status register is set to 80h. rp# low will abort the operation during block erase, programming, or lock bit configuration modes. sts in ry/by# mode remains low until the reset operation is complete. the previously altered memory contents are no longer valid since the data may be partially corrupted after programming or partially altered after an erase or lock bit configuration. a period of t phwl is required after rp# goes to logic high (v ih ) before another command can be written. rp# must be
5 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary figure 1 memory map 64k-byte block 1fffff 1f0000 31 64k-byte block 01ffff 010000 1 64k-byte block 00ffff 000000 0 32k-word block 0fffff 0f8000 31 32k-word block 00ffff 008000 1 32k-word block 007fff 000000 0 byte-wide (x8) mode word-wide (x16) mode asserted during system reset. when the system is out of reset mode, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase, programming, or lock bit configuration modes. if a cpu reset occurs with no flash memory reset, the proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. microns flash memories allow proper cpu initializa- tion following a system reset through the use of the rp# input. in this application, rp# is controlled by the same system cpu reset# signal. read query operation read query operation provides block status, cfi id string, system interface, device geometry, and ex- tended query information. read identifier codes operation this operation outputs the manufacturer code, device code, and block lock configuration codes for each block configuration (see figure 2). the system software can automatically match the device with its proper algorithms using the manufacturer and device codes. figure 2 device identifier for code memory map reserved area (subsequent blocks) reserved area block 1 lock configuration reserved area device code manufacturer code block 0 block 1 word address 0ffff 08004 08003 08002 08000 07fff 00004 00003 00002 00001 00000 block 0 lock configuration
6 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary table 1 bus operation mode rp# ce0# ce1# oe# 1 we 1 address v pp dqs 2 sts 3 notes read v ih v il v il v il v ih xxd out x 5, 6 output disable v ih v il v il v ih v ih x x high-z x standby v ih v il v ih x x x x high-z x v ih v il v ih v ih reset/power- v il x x x x x x high-z high-z 4 7 down mode read identifier v ih v il v il v il v ih see x d out high-z 4 8 codes figure 1 read query v ih v il v il v il v ih see table 5 x d out high-z 4 9 write v ih v il v il v ih v il xv pph 1 d in x 3, 10, v pph 2 11 v pph 3 note: 1. oe# = v il and we# = v il concurrently is an undefined state and should not be attempted. 2. dq refers to dq0Cdq7 if byte# is low and dq0Cdq15 if byte# is high. 3. sts in level ry/by# mode (default) is v ol when the ism is executing internal block erase, programming, or lock bit configuration algorithms. it is v oh when the ism is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or deep power-down mode. 4. high-z will be v oh with an external pull-up resistor. 5. refer to dc characteristics table. when v pp v pplk , memory contents can be read, but not altered. 6. x can be v il or v ih for control and address input pins and v pplk or v pph 1/2/3 for v pp . see the dc characteristics table for v pplk and v pph 1/2/3 voltages. 7. rp# at gnd 0.2v ensures the lowest deep power-down current. 8. see read identifier codes command section for read identifier code data. 9. see read query mode section for read query data. 10. command writes involving block erase, write, or lock bit configuration are reliably executed when v pp = v pph 1/2/3 and v cc = v cc 1/2 (see write/erase current drain table). 11. refer to table 2 for valid d in during a write operation. write write commands to the cel enables reading the device data, query, identifier codes, and inspection and clearing of the status register. in addition, when v pp = v pph 1/2/3 , block erasure, programming, and lock bit configuration can also be performed. the block erase command requires the command and address within the block to be erased. the byte/word write command requires writing the command and address of the desired location. the clear block lock bits command requires the command and an address within the whole device. set block lock bits commands require the command and address within the block to be locked. the cel is written when ce0#, ce1# (cex#), and we# are active and oe# = v ih . the address and data for a command execution are latched on the rising edge of we# or cex#, whichever goes high first. standard microprocessor write timings are used. the write operations timing diagram illustrates a write operation. command definitions v pp voltage v pplk allows read operations from the status register, identifier codes, or memory blocks. placing v pph 1/2/3 on v pp enables successful block erase, programming, and lock bit configuration operations. to select device operations, one must write specific commands into the cel. table 2 defines these commands.
7 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary table 2 command set definitions 1 first bus cycle second bus cycle scalable bus or basic cycles command command reqd oper 3 addr 4 data 5,6 oper 3 addr 4 data 5,6 notes set 2 read array scs/bcs 1 w rite x ffh read identifier scs/bcs ? 2 write x 90h read ia id 7 read query scs ? 2 write x 98h read qa qd read status register scs/bcs 2 w rite x 70h read x srd clear status register s cs/bcs 1 w rite x 50h write-to-buffer scs >2 w rite ba e8h write ba n 8, 9, 10 word/byte program scs/bcs 2 w rite x 10h/40h w rite pa pd 11, 12 block erase scs/bcs 2 w rite x 20h write ba d0h 10, 11 block erase, word/ scs/bcs 1 w rite x b0h 11 byte program suspend block erase, word/ scs/bcs 1 w rite x d0h 11 byte program resume sts pin configuration scs 2 write x b8h write x cc set block lock bit scs 2 w rite x 60h write ba 01h 13 clear block lock bits scs 2 write x 60h write x d0h 14 full chip erase scs 2 w rite x 30h write x d0h 10 note: 1. commands other than those shown above are reserved for future use and should not be used. 2. the scs is compatible with the intel ? extended command set. 3. bus operations are defined in table 1. 4. x = any valid address within the device ba = address within the block being erased or locked ia = identifier code address; see table 11 qa = query database address pa = address of memory location to be programmed 5. id = data read from query database srd = data read from status register; see table 14 for a description of the status register bits pd = data to be programmed at location pa; data is latched on the rising edge of we# cc = configuration code; see table 13 6. the upper byte of the data bus (dq8Cdq15) during command writes is a dont care in x16 operation. 7. following the read identifier codes command, read operations access manufacturer, device, and block lock codes. see read identifier codes command section for read identifier code data. 8. after the write-to-buffer command is issued, check the xsr to make sure a write buffer is available. 9. n = byte/word count argument such that the number of bytes/words to be written to the input buffer = n + 1. (n = 0 is one byte/word length, and so on.) write-to-buffer is a multicycle operation, where a byte/word count of n + 1 is written to the correct memory address (wa) with the proper data (wd). the confirm command (d0h) is expected after exactly n + 1 write cycles; any other command at that point in the sequence aborts the buffered write. writing a byte/word count outside the buffer boundary causes unexpected results and should be avoided. 10. the write-to-buffer , block erase, or full chip erase operation does not begin until a confirm command (d0h) is issued. confirm also reactivates suspended operations. 11. if a block is locked (i.e., the blocks lock bit is set to 0), wp# must be at v ih in order to perform block erase, program, and suspend operations. attempts to issue a block erase, program, or suspend operation to a locked block while wp# is v il will fail. 12. either 40h or 10h are recognized by the ism as the byte/word program setup. 13. a block lock bit can be set only while wp# is v ih . 14. wp# must be at v ih to clear block lock bits. the clear block lock bits operation simultaneously clears all block lock bits.
8 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary read array command upon initial device power-up and exiting the deep power-down mode, the default state is the read array mode. this mode is also initiated by writing the read array command to the device. the device remains available for reads until another command is written. once the ism has started block erase, program, or lock bit configuration, the device will not recognize the read array command until the ism completes its operation, unless the ism is suspended via an erase suspend or program suspend command. the read array command functions independently of the v pp voltage. read query mode command this section is related to the definition of the data structure returned by the cfi query command. sys- tem software can access this structure to gain critical information such as block size, density, x8/x16 configu- ration, and electrical specifications. once this informa- tion has been obtained, the software will know which command sets can be used to enable flash writes, block erases, and otherwise control the flash component. the query belongs to an overall specification for multiple command set and control interface descriptions called common flash interface (cfi).
9 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary query structure output the query data structure allows system software to gain critical information for controlling the flash de- vice. the devices cfi-compliant interface allows the host system to access query data. query data is always located on the lowest-order data outputs (dq0-dq7) only. the numerical offset value is the address relative to the maximum bus width supported by the device. since the maximum bus width is x16, the query table device starting address is a 10h word address. (see tables 3 and 4.) for x16 organization, the first two bytes of the query structure, q and r in ascii, appear on the low byte at word addresses 10h and 11h. this cfi-compliant device outputs 00h data on upper bytes, thus making the device output ascii q on the low byte (dq0- dq7) and 00h on the high byte (dq8-dq15). because the device is either x8 or x16 capable, the x8 data is still presented in word-relative (16-bit) addresses. however, the fill data (00h) will be driven by the upper bytes in the x16 mode. as in x16 mode, the byte address (a0) is ignored for query output so that the odd byte address (a0 high) repeats the even byte address data (a0 low). therefore, in x8 mode, using byte addressing, the device will output the sequence q, q, r, r, y, y, and so on, beginning at byte-relative address 20h. note that the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. table 4 example of query structure output device word addressing: byte byte addressing: address query data query data a16Ca1 dq15Cdq0 a7Ca0 dq7Cdq0 0010h 0051h q 20h 51h q 0011h 0052h r 21h 51h q 0012h 0059h y 22h 52h r 0013h p_idlo prvendor 23h 52h r 0014h p_idhi id # 24h 59h y 0015h plo prvendor 25h 59h y 0016h phi tbladr 26h p_idlo prvendor 0017h a_idlo altvendor 27h p_idlo id # 0018h a_idhi id # 28h p_idhi ... ... ... ... id # table 3 summary of query structure output word addressing byte addressing device type/ location query data location query data mode hex ascii hex ascii x16 device/ 10h 0051h q 20h 51h q x16 mode 11h 0052h r 21h 00h null 12h 0059h y 22h 52h "r" x16 device/ n/a 1 n/a 20h 51h q x8 mode 21h 51h q 22h 52h r note: 1. the system must drive the lowest order addresses to access all the devices array data when the device is configured in x8 mode. therefore, word addressing where lower addresses are not toggled by the system is not applicable for x8-configured devices.
10 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary table 5 query structure 1 offset subsection name description 00h manufacturer code 01h device code (ba+2)h 2 block status register block-specific information 04-0fh reserved reserved for vendor-specific information 10h cfi query identification string command set id and vendor data offset 1bh system interface information device timing and voltage information 27h device geometry definition flash device layout p 3 primary micron-specific extended query vendor-defined additional information table specific to the primary vendor algorithm note: 1. refer to the query structure output section and table 3 for the detailed definition of offset address as a function of device word width and mode. 2. ba = the beginning location of a block address (i.e., 008000h) is the beginning location of block 1 when the block size is 32k-word. 3. offset 15 defines p, which points to the primary extended query table. query structure overview the query command allows the flash component to display the cfi query structure. table 5 summarizes the structure subsections and address locations.
11 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary block status register the block status register indicates the completion of an erase operation, or whether a given block is either locked or can be accessed for program or erase operations. block erase status (bsr1) allows system software to recognize the success of the last block erase operation. after power-up, bsr1 can be used to verify that the v cc supply was not accidentally removed during an erase operation. by issuing another erase operation to the block, this bit can be reset. within each block, the block status register is accessed from word address 02h. cfi query identification string the identification string verifies whether the device supports the cfi specification. additionally, it indi- cates the specification version and vendor-specified command set(s) to be supported. table 6 block status register offset length description x16 mode (bytes) (ba + 2)h 1 01h block status register ba + 2: 0000h or 0001h bsr0 = block lock status ba + 2 (bit 0): 0 or 1 1 = locked 0 = unlocked bsr1 = block erase status ba + 2 (bit 1): 0 or 1 1 = last erase operation did not complete successfully 0 = last erase operation completed successfully bsr2Cbsr7 = reserved for future use ba + 2 (bits 2-7): 0 note: 1. ba = the beginning location of a block address (i.e., 008000h is the beginning location of block 1 in word mode.) table 7 cfi identification offset length description value (bytes) 10h 03h query-unique ascii string qry 10: 0051h 11: 0052h 12: 0059h 13h 02h primary vendor command set and control interface id code 13: 0001h 16-bit id code for vendor-specified algorithms 14: 0000h 15h 02h address for primary algorithm extended query table 15: 0031h offset value = p = 31h 16: 0000h 17h 02h alternate vendor command set and control interface id code 17: 0000h second vendor-specified algorithm supported 18: 0000h note: 0000h means none exist 19h 02h address for secondary algorithm extended query table 19: 0000h note: 0000h means none exist 1a: 0000h
12 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary table 8 system interface information offset length description value (bytes) 1bh 01h v cc logic supply minimum program/erase voltage 1b: 0027h bits 7C4 bcd volts bits 3C0 bcd 100mv 1ch 01h v cc logic supply maximum program/erase voltage 1c: 0055h bits 7C4 bcd volts bits 3C0 bcd 100mv 1dh 01h v pp [programming] supply minimum 1d: 0027h program/erase voltage bits 7C4 hex volts bits 3C0 bcd 100mv 1eh 01h v pp [programming] supply maximum 1e: 0055h program/erasevoltage bits 7C4 hex volts bits 3C0 bcd 100mv 1fh 01h typical timeout per single byte/ 1f: 0003h word program, 2 n sec (2 3 = 8) 20h 01h typical timeout for max. buffer 20: 0006h write, 2 n sec (2 6 = 64) 21h 01h typical timeout per individual 21: 000ah block erase, 2 n msec (0ah = 10d, 2 10 = 1,024) 22h 01h typical timeout for full 22: 000fh chip erase, 2 n msec (0fh = 15d, 2 15 = 32,768) 23h 01h maximum timeout for byte/word 23: 0004h program, 2 n times typical (2 4 = 16, 16 x typical) 24h 01h maximum timeout for buffer write, 24: 0004h 2 n times typical (2 4 = 16, 16 x typical) 25h 01h maximum timeout per individual 25: 0004h block erase, 2 n times typical (2 4 = 16, 16 x typical) 26h 01h maximum timeout for full chip 26: 0004h erase, 2 n times typical (2 4 = 16, 16 x typical) system interface information table 8 provides useful information to optimize the system interface software.
13 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary device geometry definition this table provides critical details of the device geometry. table 9 device geometry definition offset length description value (bytes) 27h 01h device size = 2 n in number of bytes (15h = 21d, 2 21 = 2,097,152 bytes = 2mb = 16mb) 28h 02h flash device interface description: 28: 0002h value meaning 29: 0000h 0002h x8/x16 asynchronous 2ah 02h maximum number of bytes in write buffer 2a: 0005h = 2 n 2b: 0000h (2 5 = 32) 2ch 01h number of erase block regions within 2c: 0001h device: bits 7C0 = x = number of regions within the device containing one or more contiguous erase blocks of the same size 2dh 04h erase block region information: y: 2d: 001fh bits 15C0 = y, where y + 1 = number of 2e: 0000h erase blocks of identical size within region. (1fh + 1 = 32 blocks) bits 31C16 = z, where the erase block(s) z: 2f: 0000h within this region are z 256 bytes and z is 30: 0001h the number of 256-byte clusters in an (100h = 256, 256 x 256 = 64kb) erase block.
14 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary micron-specific extended query table table 10 specifies micron-specific extended query. some flash features and commands are optional. note: 1. the variable p is a pointer which is defined at offset 15h in table 7. table 10 primary vendor-specific extended query offset length description data (bytes) (p)h 03h primary extended query table 31: 0050h unique ascii string pri 32: 0052h 33: 0049h (p+3)h 01h major version number, ascii 34: 0031h (p+4)h 01h minor version number, ascii 35: 0030h (p+5)h 04h optional feature and command support 36: 000fh bit 0 chip erase supported = yes = 1 37: 0000h bit 1 suspend erase supported = yes = 1 38: 0000h bit 2 suspend program supported = yes = 1 39: 0000h bit 3 lock/unlock supported = yes = 1 bit 4 queued erase supported = no = 0 bits 5-31 reserved for future use; undefined bits are 0 (p+9)h 01h functions supported after suspend 3a: 0001h read array, status, and query are always supported during suspended erase or program operation. this field defines other operations supported. bit 0 program supported after erase suspend = yes = 1 bits 1-7 reserved for future use; undefined bits are 0 (p+a) 02h block status register mask 3b: 0003h defines which bits in the block status register section of 3c: 0000h query are implemented. bit 0 block status register lock bit [bsr0] active = yes = 1 bit 1 block erase status bit [bsr1] active = yes = 1 bits 2-15 reserved for future use; undefined bits are 0 (p+c)h 01h v cc logic supply optimum program/erase voltage (highest 3d: 0050h performance) bits 7C4 bcd value in volts bits 3C0 bcd value in 100mv (p+d)h 01h v pp [programming] supply optimum program/erase voltage 3e: 0050h bits 7C4 hex value in volts bits 3C0 bcd value in 100mv (p+e)h reserved r eserved for future use
15 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary table 11 identifier codes code address 1 data manufacturer 000000 b0 compatibility code device code 000001 d0 block lock configuration x0002 2 ? block is unlocked dq0 = 0 ? block is locked dq0 = 1 ? reserved for future use dq2-dq7 block erase status x0002 2 ? last erase completed dq1 = 0 successfully ? last erase did not dq1 = 1 complete successfully ? reserved for future use dq2-dq7 read identifier codes command by writing the read identifier codes com- mand, the identifier code operation is initiated. following the command write, read cycles from ad- dresses shown in figure 2 (p. 5) retrieve information on the manufacturer, device, block lock configuration, and block erase status codes (see table 11 for identifier code values). to terminate the operation, write another valid command. like the read array command, the read identifier codes command functions inde- pendently of the v pp voltage. following the read identifier codes command, the information in table 11 can be read. read status register command the read status register command functions independently of the v pp voltage. it is used to determine the successful completion of programming, block era- sure, or lock bit configuration. the status register may be read by writing the read status register com- mand. once the command is written, all subsequent read operations output data from the status register, with this data being latched on the falling edge of oe# or cex#, whichever occurs last. to update the status register latch, oe# or cex# must be toggled to v ih . from time t wb after a program, block erase, set block lock bit, or clear block lock bits command sequence, only sr7 is valid until the ism completes or suspends the operation. device i/o pins dq0-dq6 and dq8- dq15 are invalid. once the operation completes or suspends (sr7 = 1), all contents of the status register are valid when read. the extended status register (xsr) may be read to determine write buffer availability (see table 15). by writing the write-to-buffer command, the xsr may be read at any time. after writing this com- mand, all subsequent read operations output data from the xsr until another valid command is written. the contents of the xsr are latched on the falling edge of oe# or cex#, whichever occurs last in the read cycle. to update the xsr latch, the write-to-buffer com- mand must be re-issued. clear status register command status register bits sr5, sr4, sr3, and sr1 are set to 1s by the ism and can only be reset by the clear status register command. these bits indicate vari- ous failure conditions (see table 14). by allowing system software to reset these bits, several operations may be performed. the status register may be polled to deter- mine if an error occurred during the sequence. to clear the status register, the clear status register com- mand is written. it functions independently of the applied v pp voltage. note that this command is not functional during block erase or program suspend modes. block erase command a block erase is initiated by a two-cycle com- mand and is executed one block at a time. a block erase setup command is written, followed by a confirm command. this command sequence re- quires appropriate sequencing and that an address within the block be erased. block preconditioning, erase, and verify are handled internally by the ism (invisible to the system). after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see figure 6). the cpu can detect block erase completion by analyzing sts in ry/by# level mode or status register bit sr7. toggle oe#, ce0#, or ce1# to update the status register. upon completion of block erase, status register bit sr5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cel remains in read status register mode until a new com- mand is issued. note: 1. a0 should be ignored in this address. the lowest- order address line is a1 in both word and byte mode. 2. x selects the specific block lock configuration code. see figure 2 for the device identifier code memory map.
16 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary this two-step command sequence of setup followed by execution ensures that block contents are not acci- dentally erased. an invalid block erase command se- quence will result in both status register bits sr4 and sr5 being set to 1. also, reliable block erasure can only occur when v cc = v cc 1/2 and v pp = v pph 1/2/3 . in the absence of these voltages, block contents are protected against erasure. if block erase is attempted while v pp v pplk , sr3 and sr5 will be set to 1. successful block erase requires that the corresponding block lock bit be cleared or that wp# ? v ih . if block erase is attempted when the corresponding block lock bit is set and wp# = v il , the block erase will fail, and sr1 and sr5 will be set to 1. full chip erase command the full chip erase command erases all un- locked blocks. after the confirm command is writ- ten, the device erases all unlocked blocks from block 0 to block 31 sequentially. block preconditioning, erase, and verify are handled internally by the ism. after the full chip erase command sequence is written to the cel, the device automatically outputs the status register data when read. the cpu can detect full chip erase completion by polling the sts pin in ry/by# level mode or status register bit sr7. once the full chip erase is complete, status register bit sr5 should be checked to see if the operation completed successfully. if an erase error occurred, the status register should be cleared before issuing the next command. the cel remains in read status register mode until a new command is issued. in the absence of these voltages, the block contents can be protected against erasure. issuing the read identifier codes com- mand or query command can inform the user of which block(s) failed to erase. this two-step command sequence of setup followed by execution ensures that block contents are not accidentally erased. an invalid full chip erase command sequence will set both status register bits sr4 and sr5 to 1. also, reliable full chip erasure can only occur when v cc = v cc 1/2 and v pp = v pph 1/2/3 . block contents can be protected against era- sure in the absence of these voltages. if full chip erase is attempted while v pp v pplk , sr3 and sr5 will be set to 1. full chip erase cannot be suspended. write-to-buffer command a write-to-buffer command sequence is initi- ated to program the flash device via the write buffer. a variable number of bytes or words can be written into the buffer and be programmed to the flash device. first, the write-to-buffer setup command is issued, along with the block address. at this point, the xsr information is loaded and xsr7 indicates that another write-to-buffer command is possible. if xsr7 = 0, the write buffer is not available. to retry, continue monitoring xsr7 by issuing the write-to-buffer setup command with the block address until xsr7 = 1. when xsr7 = 1, the buffer is ready for loading. next, a word or byte count is issued at a valid address within the block. on the next write, a device start address is given along with the write buffer data. to optimize the performance and lower power, align the start address at the beginning of a write buffer boundary. depending on the count, subsequent writes must supply addi- tional device addresses and data. once the final buffer data is given, a write con- firm command is issued. this allows the ism to begin copying the buffer data to the flash memory. if a command other than write confirm is written to the device, an invalid command/sequence error will be generated and status register bits sr5 and sr4 will be set to 1. additional buffer writes can be issued with another write-to-buffer setup command and check xsr7. refer to figure 3 for the write-to-buffer flowchart. if an error occurs during writing, the device will stop programming, and status register bit sr4 will be set to a 1 to indicate a program failure. any time a media failure occurs during a program or erase (sr4 or sr5 is set), the device will not accept any more write-to- buffer commands. additionally, if the user attempts to write past an erase block boundary with a write- to-buffer command, the device will abort program- ming and generate an invalid command/sequence error, and status register bits sr5 and sr4 will be set to 1. to clear sr4 and/or sr5, issue a clear status register command. buffered programming can only occur when v cc = v cc 1/2 and v pp = v pph 1/2/3 . if program- ming is attempted while v pp v pplk , status register bits sr4 and sr5 will be set to 1. programming attempts with invalid v cc and v pp voltages produce spurious results and should not be attempted. finally, successful programming requires that the corresponding block lock bit be cleared, or wp# = v ih . if a buffer write command is issued when the corresponding block lock bit is set and wp# = v il , sr1 and sr4 will be set to 1. byte/word program commands the byte/word programming is executed by a two- cycle command sequence. after the byte/word pro- gram setup, a second write is needed to specify the address and data (latched on the rising edge of we#). next, the ism takes over to control the program and verify algorithms internally. once the write sequence is written, the device automatically outputs status register data when read. the cpu can detect the completion of the program event by analyzing the sts in ry/by# level
17 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary mode or status register bit sr7. upon programming completion, status register bit sr4 should be checked. if a programming error is detected, the status register should be cleared. the ism verify only detects errors for 1s that do not successfully program to 0s. the cel remains in read status register mode until it receives another command. refer to figure 4 for the single word/byte program flowchart. also, reliable byte/ word programming can only occur when v cc = v cc 1/2 and v pp = v pph 1/2/3 . in the absence of this high voltage, contents are protected against programming. if a byte/ word program is tried while v pp v pplk , status register bits sr4 and sr3 will be set to 1. successful byte/word programming requires that the corresponding block lock bit be cleared. if a byte/word program is attempted when the corresponding block lock bit is set and wp# = v il , sr1 and sr4 will be set to 1. sts configuration command using the sts configuration command, the sts pin can be configured to different states. once configured, it remains in that configuration until an- other configuration command is issued or rp# is low. initially, the sts pin defaults to ry/by# level operation. sts low indicates that the state machine is busy, while sts high indicates that the state machine is ready for a new operation or is suspended. to change the sts pin to other modes, the sts configuration command must be issued followed by the desired configuration code. the three alternate pulse-mode configurations may be used as a system interrupt as described in table 13. with these configu- rations, bit 0 controls erase complete interrupt pulse, and bit 1 controls write complete interrupt pulse. once the device is configured in one of the pulse modes, the sts pin pulses low with a typical pulse width of 250ns. issuing the 00h configuration code with the con- figuration command resets the sts pin to the default ry/by# level mode. table 13 explains configu- ration coding definitions. the configuration com- mand may only be given when the device is not busy or suspended. check sr7 for device status. an invalid configuration code will result in status register bits sr4 and sr5 being set to 1. block erase suspend command this command allows block erase interruption to read or program data in another block of memory. right after starting the block erase process, writing the block erase suspend command requests that the ism suspend the block erase sequence at a predeter- mined point in the algorithm. when read after the block erase suspend command is written, the device outputs the status register. polling status register bit sr7 can determine when the block erase opera- tion has been suspended. when sr7 = 1, sr6 should also be set to 1, indicating that the device is in the erase suspend mode. sts in ry/by# level mode will also transition to v oh . specification t les defines the block erase suspend latency. at this point, a read array command can be written to read data from blocks other than that which is suspended. a program command sequence can also be issued during erase suspend to program data in other blocks. using the program suspend command (see program suspend command section), a program operation can also be suspended. during a program operation with block erase sus- pended, status register bit sr7 will return to 0, and sts in ry/by# mode will transition to v ol . however, sr6 will remain 1 to indicate block erase suspend status. read status register and block erase re- sume are the only other valid commands while block erase is suspended. once a block erase resume command is written to the flash memory, the ism will continue the block erase process. status register bits sr6 and sr7 will automatically clear, and sts in ry/by# mode will return to v ol . once the erase resume command is written, the device automatically outputs status register data when read (see figure 8). v pp must remain at v pph 1/2/3 and v cc must remain at v cc 1/2 (the same v pp and v cc levels used for block erase) while block erase is suspended. rp# ? v ih . block erase cannot resume until program operations initiated during block erase suspend have completed. program suspend command the program suspend command enables pro- gram interruption to read data in other flash memory locations. after starting the programming process, writing the program suspend command requests that the ism suspend the program sequence at a predetermined point in the algorithm. once the pro- gram suspend command is written, the device con- tinues to output status register data when read. polling status register bit sr7 can determine when the program- ming operation has been suspended. when sr7 = 1, sr2 should also be set to 1 to indicate that the device is in the program suspend mode. sts in ry/by# level mode will also transition to v oh . note that t lps defines the program suspend latency. a read array com- mand can be written to read data from locations other than that which is suspended. while programming is suspended, the only other valid commands are read status register and program resume. once a program resume command is written, the ism will continue the programming process. then status register bits sr2 and sr7 will automatically clear and sts in
18 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary ry/by# mode will return to v ol . once a program resume command is written, the device automatically outputs status register data when read. v pp must remain at v pph 1/2/3 and v cc must remain at v cc 1/2 while in program suspend mode. rp# must also remain at v ih (the same rp# level used for programming). refer to figure 5 for the program suspend/resume flow- chart. set block lock bits command a flexible block locking and unlocking scheme is enabled via a combination of block lock bits. the block lock bits gate program and erase operations. with wp# = v ih , individual block lock bits can be set using the set block lock bits command. set block lock bits is started using a two-cycle command sequence. the set block lock bits setup along with appropriate block address is written, fol- lowed by the set block lock bits confirm and an address within the block to be locked. the ism then controls the set lock bit algorithm. once the sequence is written, the device automatically outputs status register data when read. the cpu then can detect the completion of the set lock bit event by analyzing sts in ry/by# level mode or status register bit sr7. upon completion of the set block lock bits operation, status register bit sr4 should be checked. if an error is detected, the status register should be cleared. the cel will remain in the read status register mode until a new command is issued. this two-step sequence of setup followed by execu- tion ensures that lock bits are not accidentally set. an invalid set block lock bits command will result in status register bits sr4 and sr5 being set to 1. also, reliable operations occur only when v cc = v cc 1/2 and v pp = v pph 1/2/3 . if these voltages are absent, lock bit contents are protected against alteration. a successful set block lock bits operation requires that wp# = v ih . if it is attempted with wp# = v il , the operation will fail, and sr1 and sr4 will be set to 1. see table 12 for write protection alternatives and refer to figure 8 for the set block lock bits flowchart. clear block lock bits command the clear block lock bits command can clear all set block lock bits in parallel. this command is valid only when wp# = v ih . the clear block lock bits operation is started using a two-cycle command se- quence. a clear block lock bits setup command is written, followed by a confirm command. then, the device automatically outputs status register data when read (see figure 10). once completed, the cpu can detect the completion of the clear block lock bits event by analyzing sts in ry/by# level mode or status register bit sr7. this two-step sequence of setup followed by execu- tion ensures that block lock bits are not accidentally cleared. an invalid clear block lock bits command sequence will result in status register bits sr4 and sr5 being set to 1. also, a reliable clear block lock bits operation can only occur when v cc = v cc 1/2 and v pp = v pph 1/2/3 . if a clear block lock bits operation is attempted while v pp v pplk , sr3 and sr5 will be set to 1. if these voltages are absent, the block lock bits contents are protected against alteration. when a clear block lock bits operation is aborted due to v pp or v cc transitioning out of valid range and rp# or wp# active transition, block lock bit values become undetermined. then, a repeat of clear block lock bits is required to initialize block lock bit contents to known values. once the operation is complete, status register bit sr5 should be checked. also, if a clear block lock bits error is detected, the status register should be cleared. the cel will remain in read status register mode until another command is issued.
19 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary table 12 write protection alternatives operation block wp# effect lock bit program and 0 v il or v ih block erase and programming enabled block erase 1 v il block is locked; block erase and programming disabled v ih block lock bit override; block erase and programming enabled full chip erase 0,1 v il all unlocked blocks are erased xv ih block lock bit override; all blocks are erased set or clear x v il set or clear block lock bits disabled block lock bits v ih set or clear block lock bits enabled table 13 configuration coding definitions reserved pulse on pulse on write complete erase complete bits 7C2 bit 1 bit 0 dq7Cdq2 are reserved for future use. default ry/by# level mode (dq1/dq0 = 00) used to control hold to a memory controller to prevent accessing a flash memory subsystem while any flash devices ism is busy. configuration 01 er int, pulse mode 1 used to generate a system interrupt pulse when any flash device in an array has completed a block erase or sequence of queued block erases; helpful for reformatting blocks after file system free space reclamation or cleanup. configuration 10 pr int, pulse mode 1 used to generate a system interrupt pulse when any flash device in an array has completed a program operation. provides highest performance for servicing continuous buffer write operations. configuration er/pr int, pulse mode 1 used to generate system interrupts to trigger the servicing of flash arrays when either erase or flash program operations are completed when a common interrupt service routine is desired. dq7Cdq2 = reserved dq1/dq0 = sts pin configuration codes 00 = default, ry/by# level mode (device ready) indication 01 = pulse on erase complete 10 = pulse on flash program complete 11 = pulse on erase or program complete configuration codes 01b, 10b, and 11b are all pulse modes such that the sts pin pulses low then high when the operation indicated by the given configuration is completed. configuration command sequences for sts pin configuration (masking bits dq7Cdq2 to 00h) are as follows: default ry/by# level mode: b8h, 00h er int (erase interrupt): b8h, 01h pulse on erase complete pr int (program interrupt): b8h, 02h pulse on flash program complete er/pr int (erase or program interrupt): b8h, 03h pulse on erase or program complete note: 1. when the device is configured in one of the pulse modes, the sts pin pulses low with a typical pulse width of 250ns.
20 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary table 14 status register definition isms ess eclbs pslbs v pp s pss dps r 76543210 status register bit (sr) description sr7 = internal state machine status (isms) check sts in ry/by# mode or sr7 to determine 1 = ready bl ock erase, programming, or lock bit configuration 0 = busy completion. sr6-sr0 are invalid when sr7 = 0. sr6 = erase suspend status (ess) 1 = block erase suspended 0 = block erase in progress/completed sr5 = erase and clear lock bits status (eclbs) if both sr5 and sr4 are 1s after a block erase 1 = error in block erasure or clear lock bits or lock bit configuration attempt, an improper 0 = successful block erase or clear lock bits command sequence was entered. sr4 = program and set lock bits status (pslbs) 1 = error in program or block lock bits 0 = successful program or set block lock bits sr3 = v pp status (v pp s) sr3 does not provide a continuous indication of 1 = v pp low detect, operation abort v pp level. the ism interrogates and indicates the 0 = v pp ok v pp level only after a block erase, program, or lock bit configuration operation. sr3 reports accurate feedback only when v pp = v pph 1/2/3 . sr2 = program suspend status (pss) 1 = program suspended 0 = program in progress/completed sr1 = device protect status (dps) sr1 does not provide a continuous indication of 1 = block lock bit and/or block lock bit values. the ism interrogates the wp# lock detected, operation abort block lock bit and wp# only after a block erase, 0 = unlock program, or lock bit configuration operation. it informs the system, depending on the attempted operation, if the block lock bit is set. sr0 = reserved for future enhancements sr0 is reserved for future use and should be masked when polling the status register. status register bit (xsr) description xsr7 = write buffer status (wbs) after a write-to-buffer command, xsr7 indicates 1 = write-to-buffer available that a write-to-buffer command is possible. 0 = write-to-buffer not available xsr6-0 = reserved for future enhancements sr6Csr0 are reserved for future use and should be masked when polling the status register. table 15 extended status register definition (xsr) wbsrrrrrrr 76543210
21 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary figure 3 write-to-buffer flowchart yes no no no yes set timeout start 0 1 no read extended status register issue write command eh8, block address xr7= write buffer timeout? write word or byte count, block address write buffer data start address x = 0 check x = n? abort buffer write command? write to another block address buffer write-to- flash aborted no write next buffer data, device address x = x + 1 buffer write-to-flash confirm d0h another buffer write? read status register sr7= buffer write-to-flash complete suspend write? issue read status command 0 yes suspend write loop 1 yes full status check if desired bus operation command comments write write-to- data = e8h buffer block address read xsr 7 = valid addr = x standby check xsr 7 1 = write buffer available 0 = write buffer not available write 1,2 data = n = word/byte count n = 0 corresponds to count = 1 addr = block address write 3,4 data = write buffer data addr = device start address write 5,6 data = write buffer data addr = device address write buffer data = d0h write-to- addr = x flash confirm read status register data with the device enabled, oe# low updates sr addr = x standby check sr7 1 = ism ready 0 = ism busy full status check can be done after all erase and write sequences complete. write ffh after the last operation to reset the device to read array mode. note: 1. byte or word count values on dq0-dq7 are loaded into the count register. count ranges on this device for byte mode are n = 00h to 1fh and for word mode are n = 0000h to 000fh. 2. the device now outputs the status register when read (xsr is no longer available). 3. write buffer contents will be programmed at the device start address or destination flash address. 4. align the start address on a write buffer boundary for maximum programming performance (i.e., a4-a0 of the start address = 0). 5. the device aborts the write-to-buffer command if the current address is outside of the original block address. 6. the status register indicates an improper command sequence if the write-to-buffer command is aborted. follow this with a clear status register command.
22 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary figure 4 single byte/word program flowchart write 40h address start read status register write data and address sr7= suspend byte/word program full status check if desired sr4= byte/word program successful yes sr1= sr3= read status register data (see above) voltage range error device protect error programming error 0 0 0 1 1 1 no 0 byte/word program complete full status check procedure 1 suspend byte/ word program loop bus operation command comments write setup byte/ data = 40h word addr = location to be program programmed write byte/word data = data to be program programmed addr = location to be programmed read status register data standby check sr7 1 = ism ready 0 = ism busy repeat for subsequent programming operations. sr full status check can be done after each program operation or after a sequence of programming operations. write ffh after the last program operation to place device in read. bus operation command comments standby check sr3 1 = programming voltage error detect standby check sr1 1 = device protect detect rp# = v ih , block lock bit is set. only required for systems implement- ing lock bit configu- ration standby check sr4 1 = programming error sr4, sr3, and sr1 are only cleared by the clear status register command in cases where multiple locations are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery.
23 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary write b0h read status register write ffh sr7 = read data array sr2 = programming complete 1 programming resumed done reading write d0h write ffh read data array 0 no yes start 0 figure 5 program suspend/resume flowchart bus operation command comments write program data = b0h suspend addr = x read status register data addr = x standby check sr7 1 - ism ready 0 = ism busy standby check sr6 1 = programming suspended 0 = programming completed write read data = ffh array addr = x read read array location other than that being programmed write program data = d0h resume addr = x
24 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary figure 6 block erase flowchart bus operation command comments write erase data = 28h or 20h block addr = block address read xsr7 = valid addr = x write erase data = d0h confirm addr = x read status register data with the device enabled, oe# low updates sr addr = x standby check sr7 1 = ism ready 0 = ism busy full status check can be done after all erase and write sequences complete. write ffh after the last operation to reset the device to read array mode. read status register erase flash block complete sr7 = full status check if desired suspend erase issue single block erase command 20h, block address 0 yes no 1 suspend erase loop start write confirm d0h block address
25 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary write b0h read status register sr7 = sr6 = done? write d0h write ffh read data array 0 0 no yes 1 1 read or program? read program program loop read array data start block erase complete block erase resumed figure 7 block erase suspend/resume flowchart bus operation command comments write erase data = b0h suspend addr = x read status register data addr = x standby check sr7 1 - ism ready 0 = ism busy standby check sr6 1 = block erase suspended 0 = block erase completed write erase data = d0h resume addr = x
26 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary write 60h block/device address start read status register write 01h block/device address sr7= full status check if desired sr4= set block lock bits complete sr1= sr3= read status register data (see above) voltage range error device protect error set block lock bits error 0 0 0 0 1 1 1 sr4, 5= command sequence error 1 0 set block lock bits complete full status check procedure 1 figure 8 set block lock bits flowchart bus operation command comments write clear block data = 60h lock bits addr = x setup write set block data = 01h lock bits addr = x confirm read status register data standby check sr7 1 = ism ready 0 = ism busy full status check can be done after each set block lock bits operation or a sequence of block lock bits set. write ffh after the last set block lock bits operation to place the device in array mode. bus operation command comments standby check sr3 1 = programming voltage error detect standby check sr1 1 = device protect detect wp# = v il standby check sr4, sr5 both 1 = command sequence error standby check sr5 1 = set block lock bits sr5, sr4, sr3, and sr1 are only cleared by the clear register command in cases where multiple lock bits are set full status. if an error is detected, clear the status register before attempting retry or other error recovery.
27 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary write 60h start read status register write d0h sr7 = full status check if desired sr5 = clear block lock bits complete sr1 = sr3 = read status register data (see above) voltage range error device protect error clear block lock bits error 0 0 0 0 1 1 1 sr4, sr5 = command sequence error 1 0 clear block lock bits complete full status check procedure 1 figure 9 clear block lock bits flowchart bus operation command comments write clear block data = 60h lock bits addr = x setup write clear block data = d0h lock bits addr = x confirm read status register data standby check sr7 1 = ism ready 0 = ism busy write ffh after the clear block lock bits operation to place device in read array mode. bus operation command comments standby check sr3 1 = programming voltage error detect standby check sr1 1 = device protect detect wp# = v il standby check sr4, sr5 both 1 = command sequence error standby check sr5 1 = clear block lock bits error sr5, sr4, sr3, and sr1 are only cleared by the clear status register command. if an error is detected, clear the status register before attempt- ing retry or other error recovery.
28 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary design considerations three-line output control this device has three control inputs to provide multiple memory connections: ce0#, ce1#, and oe#. three-line control affords (1) lowest possible memory power dissipation; and (2) data bus conten- tion avoidance. to use these control inputs optimally, an address decoder should enable cex#, while oe# should be connected to all memory devices and the systems read# control line. this ensures that only selected memory devices have active outputs, while deselected memory devices are in standby mode. rp# should be connected to the system powergood signal to pre- vent unintended writes during system power transi- tions. powergood should also toggle during system reset. sts and ism polling the open drain output pin sts should be connected to v cc by a pull-up resistor to provide a hardware form of detecting block erase, program, and lock bit configu- ration completion. in default mode, it transitions low during execution of these commands and returns to v oh when the ism has finished executing the internal algorithm. see sts configuration command section for alternate sts configurations. sts can be connected to an interrupt input of the system cpu or controller. sts is active at all times. in the default mode, sts is also v oh during block erase suspend or reset/power-down. power supply decoupling flash memory power switching characteristics re- quire careful device decoupling. active current levels, standby current levels, and transient peaks produced by falling and rising edges of cex# and oe# are areas of consideration. two-line control and proper decoupling capacitor selection can suppress transient voltage peaks. each device should have a 0.1f ceramic capacitor connected between its v cc and gnd and v pp and gnd. these high-frequency, low-inductance capacitors should be placed as close as possible to package leads. in addition, for every eight devices, a 4.7f electrolytic capacitor should be placed at the arrays power supply connection between v cc and gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductance. v cc , v pp , rp# transitions if rp# v ih , or if v pp or v cc fall outside of a valid voltage range (v cc 1/2 and v pph 1/2/3 ), block erase, pro- gram, and lock bit configuration are not guaranteed. if v pp error is detected, status register bits sr3 and sr4 or sr5 are set to 1. if rp# transitions to v il during block erase, program, or lock bit configuration, sts in ry/by# level mode will remain low until the reset operation is complete. then, the operation will abort and the device will enter deep power-down. because the aborted operation may leave data partially altered, the command sequence must be repeated after normal operation is restored. power-up/down protection this device provides protection against accidental block erase, programming, or lock bit configuration during power transitions. system designers must guard against spurious writes for v cc voltages above v lko when v pp is active. since both we# and cex# must be low for a command write, driving either input signal to v ih will inhibit writes. the cels two-step command sequence archi- tecture provides an added level of protection against data alteration. in-system block lock and unlock pro- vides additional protection during power-up by pro- hibiting block erase and program operations. rp# = v il disables the device, regardless of its control inputs states.
29 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary temperature and recommended dc operating conditions note: 1 parameter/condition symbol min max units notes operating temperature commercial ambient temperature t a 0 +70 oc extended ambient temperature -40 +85 oc v cc supply voltage v cc 1 2.7 3.6 v (2.7v to 3.6v) v cc supply voltage v cc 2 3.0 3.6 v (3.3v 0.3v) input leakage current v cc = v cc 1/2 (max) i l 0.5 a 2 v in = v cc 1/2 or gnd output leakage current v cc = v cc 1/2 (max) i oz 0.5 a 2 v out = v cc 1/2 or gnd output voltage levels (ttl) v cc = v cc 1/2 (min) output high voltage v oh 1 2.4 v 3, 4 (i ol = 5.8ma) output low voltage v ol 0.4 v (i oh = C2.5ma) output high voltage (cmos) v cc = v cc 1/2 (min) v oh 2 0.85 v 3, 4 i oh = C2.5ma v cc v cc = v cc 1/2 (min) v cc - 0.4 v i oh = C100a input high voltage v ih 3.3 v cc + 0.5 v 5 input low voltage v il -0.5 0.8 v 4 absolute maximum ratings voltage on v cc supply relative to vss .......................... -0.2v to v cc + 0.5v* voltage on v pp voltage relative to vss during block erase, flash write, and lock bit configuration ......... -0.2v to +7.0v** output short circuit current ....................... 100 ma ? voltage on any pin (except v cc and v pp ) relative to vss ......................... -0.5v to v cc + 0.5v* temperature under bias: commercial ......................................... 0oc to +70oc extended .......................................... -40oc to +85oc storage temperature ......................... -65oc to +125oc * all specified voltages are with respect to vss (gnd). minimum dc voltage is -0.5v on input/output pins and -0.2v on v cc and v pp pins. during transitions, this level may undershoot to -2.0v for periods < 20ns. maximum dc voltage on input/output pins and v cc is v cc + 0.5v which, during transitions, may overshoot to v cc + 2.0v for periods < 20ns. **maximum dc voltage on v pp may overshoot to +7.0v for periods < 20ns. ? output shorted for no more than one second. no more than one output shorted at a time. note: 1. device operations in the v cc voltage ranges not covered in the table produce spurious results and should not be attempted. 2. all currents are in rms unless otherwise noted. typical values at nominal v cc voltage and t a = +25oc. these currents are valid for all product versions (packages and speeds). 3. includes sts in ry/by# level mode. 4. sampled, not 100% tested. 5. cmos inputs are either v cc 0.2v or gnd 0.2v. ttl inputs are either v il or v ih .
30 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary dc electrical characteristics commercial temperature (0oc t a +70oc) and extended temperature (-40oc t a +85oc) parameter/condition symbol typ max units notes read current: ttl input levels v cc = v cc 1/2 (max) i cc 1 30 ma cex# = v il ; f = 5 mhz; i out = 0ma read current: cmos input levels v cc = v cc 1/2 (max) i cc 2 25 ma 1, 3, 4 cex# = gnd; f = 5 mhz; i out = 0ma standby current: ttl input levels v cc = v cc 1/2 (max) i cc 3 14ma cex# = rp# = v ih standby current: cmos input levels v cc = v cc 1/2 (max) i cc 4 20 100 a 1, 2, 3 cex# = rp# = v cc 0.2v deep power-down current: v cc supply i cc 5 115a1 rp# = gnd 0.2v; out (ry/by#) = 0ma standby read current: v pp supply i pp 1 2 15 a 1 deep power-down current: v pp supply i pp 2 0.1 5 a 1 rp# = gnd 0.2v v pp lockout voltage v pplk 1.5 v 5, 6 v pp voltage v pph 1 2.7 3.6 v 6, 7 v pp voltage v pph 2 3.0 3.6 v 6, 7 v pp voltage v pph 3 4.5 5.5 v 6, 7 v cc lockout voltage v cclk 2.0 v 8 note: 1. all currents are in rms unless otherwise noted. typical values at nominal v cc voltage and t a = +25oc. these currents are valid for all product versions (packages and speeds). 2. includes sts in ry/by# level mode. 3. cmos inputs are either v cc 0.2v or gnd 0.2v. ttl inputs are either v il or v ih . 4. automatic power savings (aps) reduces typical i ccr to 3ma at 2.7v and 3.3v v cc static operation. 5. sampled, not 100% tested. 6. refer to read operations timing diagram. 7. refer to ac characteristics C read-only operations. if v cc is in the range of 2.7v to 3.6v (v cc 1 ), then v pp must be in the range of 2.7v to 3.6v (v pph 1 ) or 4.5v to 5.5v (v pph 3 ). if v cc is in the range of 3.0v to 3.6v (v cc 2 ), then v pp must be in the range of 3.0v to 3.6v (v pph 2 ) or 4.5v to 5.5v (v pph 3 ). 8. with v cc v lko , flash memory writes are inhibited. capacitance t a = +25oc, f = 1 mhz parameter symbol typ max units notes input capacitance: v in = 0.0v c in 68pf output capacitance: v out = 0.0v c io 812pf
31 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary table 16 valid v pp /v cc voltage v cc voltage v pp voltage v cc 1 = 2.7v to 3.6v v pph 1 = 2.7v to 3.6v, v pph 2 = 3.0v to 3.6v, or v pph 3 = 4.5v to 5.5v v cc 2 = 3.0v to 3.6v v pph 2 = 3.0v to 3.6v or v pph 3 = 4.5v to 5.5v output test points input 1.35v 1.35v 2.7v 0.0v ac test inputs are driven at 2.7v for a logic 1 and 0.0v for a logic 0. input timing begins and output timing ends at 1.35v. input rise and fall times (10% to 90%) < 10ns. transient input/output reference waveform for v cc = 2.7vC3.6v output test points input 1.5v 1.5v 3.0v 0.0v ac test inputs are driven at 3.0v for a logic 1 and 0.0v for a logic 0. input timing begins and output timing ends at 1.5v. input rise and fall times (10% to 90%) < 10ns. transient input/output reference waveform for v cc = 3.3v 0.3v (high-speed testing configuration) device under test out r l = 3.3k w 1n914 1.3v c l 0608_16 note: c l includes jig capacitance. transient equivalent testing load circuit test configuration capacitance loading value test configuration c l (pf) v cc = 3.3v 0.3v, 2.7v to 3.6v 50
32 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary ac characteristics C read-only operations 1 note 1; commercial temperature (0oc t a +70oc) and extended temperature (-40oc t a +85oc) 3.3v 0.3v v cc 2.7vC3.6v v cc -75 -10 parameter symbol min max min max units notes read/write cycle time 1 t rc 75 100 ns address to output delay t aa 75 100 ns 2 cex# to output delay t ace 75 100 ns 3 oe# to output delay t aoe 45 50 ns 3 rp# high to output delay t rwh 600 600 ns cex# to output in low-z t oec 0 0 ns 4 oe# to output in low-z t oeo 0 0 ns 4 cex# high to output in high-z t odc 50 50 ns 4 oe# high to output in high-z t odo 20 20 ns 4 output hold from address, cex#, or oe# change, t oh 0 0 ns 4 whichever occurs first cex# low to byte# high or low t cb 5 5 ns 4 byte# to output delay t aby 100 120 ns 4 byte# to output in high-z t odb 30 30 ns 4 note: 1. see read, write, and reset timing diagrams for testing characteristics. 2. see ac input/output reference waveform for maximum allowable input slew rate. 3. oe# may be delayed up to t ace - t aoe after the falling edge of cex# without impact on t ace. 4. sampled, not 100% tested.
33 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary read operations cex# addresses oe# dq0-dq15 we# rp# v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol address stable t rc byte v ih v il t aa t ace t aoe t oeo t odb t rwh t oec t cb t aby t odc t odo v cc valid output dont care t oh high-z high-z -75 -10 symbol min max min max units timing parameters -75 -10 symbol min max min max units t rc 75 100 ns t aa 75 100 ns t ace 75 100 ns t aoe 45 50 n s t rwh 600 600 ns t oec 0 0 ns t oeo 0 0 ns t odc 50 50 n s t odo 20 20 ns t oh 0 0 t cb 5 5 ns t aby 100 120 ns t odb 30 30 n s
34 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary write/erase current drain commercial temperature (0oc t a +70oc) and extended temperature (-40oc t a +85oc) parameter/condition symbol typ max units notes program or set lock bit current: v pp supply i pp 3 15 a 1, 2 v pp = v pph 1/2/3 block erase or clear block lock bits current: v pp supply i pp 4 15 a 1, 2 v pp = v pph 1/2/3 program suspend or block erase suspend current: v pp supply i pp 5 10 15 a 1 v pp = v pph 1/2/3 programming and set lock bit current: v cc supply i cc 6 95 ma 1, 2 v pp = v pph 1/2/3 block erase or clear block lock bits current: v cc supply i cc 7 55 ma 1, 2 v pp = v pph 1/2/3 program suspend or block erase suspend current: v cc supply i cc 8 1 6 ma 1, 3 cex# = v ih note: 1. all currents are in rms unless otherwise noted. typical values at nominal v cc voltage and t a = +25oc. these currents are valid for all product versions (packages and speeds). 2. sampled, not 100% tested. 3. i cc 8 is specified with the device deselected. if read or programmed while in erase suspend mode, the devices current is the sum of i cc 8 and i cc 2 or i cc 6 .
35 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary ac characteristics C write operations notes: 1, 2; commercial temperature (0oc t a +70oc) and extended temperature (-40oc t a +85oc) 3.3v 0.3v v cc 2.7vC3.6v v cc -75 -10 parameter symbol min max min max units notes rp# high recovery to we# (cex#) going low t rs 1 1 s 3 cex# setup to we# going low t cs 10 10 ns we# setup to cex# going low t ws 0 0 ns we# pulse width t wp 50 50 ns cex# pulse width t cp 70 70 ns data setup to we# (cex#) going high t ds 50 50 ns 4 address setup to we# (cex#) going high t as 50 50 ns 4 cex# hold from we# high t ch 10 10 ns we# hold from cex# high t wh 0 0 ns data hold from we# (cex#) high t dh 5 5 ns address hold from we# (cex#) high t ah 5 5 ns pulse width high t wph 30 25 ns cex# pulse width high t cph 25 25 ns wp# v ih setup to we# (cex#) going high t wps 100 100 ns v pp setup to we# (cex#) going high t vps 100 100 ns 3 write recovery before read t wr 0 0 ns we# high to sts in ry/by# low t sts 100 100 ns we# (cex#) high to busy status (sr7 = 0) t wb 100 100 ns 3, 5 wp# v ih hold from valid srd t qvsl 0 0 ns 3, 5 v pp hold from valid srd, sts in ry#/by# high t vph 0 0 ns 3, 5 note: 1. read timing characteristics during block erase, program, and lock bit configuration operations are the same as during read-only operations. refer to ac characteristics C read-only operations. 2. see read, write, and reset timing diagrams for testing characteristics. 3. sampled, not 100% tested. 4. refer to table 2 for valid a in and d in for block erase, program, or lock bit configuration. 5. v pp should be at v pph 1/2/3 until determination of block erase, program, or lock bit configuration success (sr1/3/4/5 = 0).
36 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary erase, write, and lock bit configuration performance notes: 1, 2 3.3v 0.3v v cc 2.7vC3.6v v cc parameter symbol typ 3 max 4 typ 3 max 4 units notes byte/word program time t wed1 5.66 250 5.8 250 s 5 (using write buffer) per byte program time t wed2 19.51 250 18.0 160 s 6 (without write buffer) per word program time t wed3 21.75 250 20.0 190 s 6 (without write buffer) block program time t wed4 1.6 16.5 1.2 2.0 sec 6 (byte mode) block program time t wed5 0.89 8.2 0.7 1.0 sec 6 (word mode) block program time t wed6 0.36 4.1 0.37 4.0 sec 6 (using write buffer) block erase time t wed7 0.55 20 0.56 6.0 sec 6 full chip erase time t wed8 17.6 320 17.9 190 sec set lock bit time t wed9 22.75 250 20.0 190 s 6 clear block lock bits time t wed10 0.55 10 0.56 6.0 sec 6 program suspend latency time to read t lps 7.1 10 7.2 10 s erase suspend latency time to read t les 15.2 21.1 15.5 21.5 s note: 1. these performance numbers are valid for all speed versions. 2. sampled, but not 100% tested. 3. typical values measured at t a = +25oc and nominal voltages. assumes corresponding lock bits are not set. subject to change based on device characterization. 4. maximum values represent less than 1% of units exposed to greater than 100,000 cycles. 5. uses whole buffer. 6. excludes system-level overhead.
37 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary cex# (we#) 7 addresses oe# dq0-dq15 undefined we# (cex#) wp# v ih v il a in v pp v ih v il rp# v ih v il v pplk v pph2, 1 v ih v il v ih v il v ih v il v ih v il a in d in d in t as note 2 note 1 note 3 note 4 note 5 note 6 t rs t ch [ t wh] t wr t wb t ah t cs [ t ws] t wph t wp [ t cp] t sts t ds t dh v il sts v ih v il valid srd d in t wps t qvsl t vps t vph write operations -75 -10 symbol min max min max units timing parameters -75 -10 symbol min max min max units t rs 1 1 s t cs 10 10 n s t ws 0 0 ns t wp 50 50 n s t cp 70 70 n s t d s 50 50 n s t a s 50 50 n s t c h 10 10 n s t wh 0 0 ns t dh 5 5 ns t ah 5 5 ns t wph 30 30 ns t wps 100 100 ns t vps 100 100 ns t wr 0 0 ns t sts 100 100 ns t wb 100 100 ns t qvsl 0 0 ns t vph 0 0 ns note: 1. vcc power-up and standby. 2. write block erase or program setup. 3. write block erase confirm or valid address and data. 4. automated erase and program delay. 5. read status register data. 6. write read array command. 7. cex# is the latter of ce0# and ce1# low or the first of ce0# or ce1# high.
38 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary reset ac specifications note: 1 2.7vC3.6v v cc 3.3v 0.3v v cc parameter symbol min max min max units notes rp# pulse low time t plph 100 100 ns (if rp# is tied to v cc , this specification is not applicable) rp# low to reset during block erase, t plrh 20 20 s 2, 3 program, or lock bit configuration v cc at 2.7v to rp# high t 3vph 50 50 s v cc at 3.0v to rp# high reset operation v cc rp# v ih v il v 0 v cc1 sts v ih v il t plrh t plph t 3vph note: 1. these specifications are valid for all product versions (packages and speeds). 2. if rp# is asserted while a block erase, program, or lock bit configuration operation is not executing, the reset will complete within t plph. 3. a reset time, t phqv, is required from the latter of sts in ry/by# mode or rp# going high until outputs are valid.
39 2 meg x 8 /1 meg x 16 even-sectored flash memory micron technology, inc., reserves the right to change products or specifications without notice. MT28F160S3_2 C rev. 8/00 ?2000, micron technology, inc. 2 meg x 8/1 meg x 16 smart 3 even-sectored flash preliminary 56-pin plastic tsop i note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01 per side. see detail a .007 (0.18) .0197 (0.50) .554 (14.07) .010 (0.25) .010 (0.25) 1 28 29 56 .047 (1.20) max .548 (13.92) .005 (0.13) .006 (0.15) typ .727 (18.47) .795 (20.20) .780 (19.80) .721 (18.31) typ .002 (0.05) detail a .016 (0.40) .024 (0.60) .0315 (0.80) .008 (0.20) .004 (0.10) .010 (0.25) plane gage pin #1 index 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron is a registered trademark of micron technology, inc. intel is a registered trademark of intel corporation.

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